This invention relates to variable delay circuitry, and more particularly to delay circuitry that is programmable with respect to the amount of signal delay provided.
Programmable logic devices (“PLDs”) are an example of circuitry in which it is helpful to include variable delay circuitry. Such circuitry in a PLD may be used to adjust the delay between the arrival of an input data signal on the device and delivery of that data signal to core (e.g., programmable logic) circuitry of the device. The input data signal may or may not be registered in an input/output (“I/O”) cell of the device, and from the I/O cell the data signal may be registered or not registered when it reaches the core of the device. The data signal may need to be delayed in the course of this handling to improve its timing relative to other signals on the device (e.g., clock signals). How the signal is used (e.g., whether and where it is registered) can affect how much and how precisely the data signal needs to be delayed. Some uses of the data signal may need relatively large amounts of delay, but within a relatively broad range of acceptable values. Other uses of the data signal may need only relatively small amounts of delay, but with greater precision. Still other uses of the data signal may need large amounts of delay and precision with regard to that delay.